Data and clock recovery circuitry rely on phase detectors to calculate and adjust for frequency shifts in feedback signals. Being able to correct the phase shift in feedback signals can be paramount in applications ranging from motor control and servo mechanisms to communications and automatic test equipment (“ATE”). These electronic applications utilize phase-locked loops to generate and maintain a signal in a fixed phase compared to a reference signal. For example, ATE often uses data recovery data lock loops (DRDLL) to ensure timing accuracy.
Typical topologies for phase detectors utilize a linear multiplier or a bang-bang type configuration. A linear multiplier generates a low-frequency signal whose amplitude is related to the phase difference, or phase error, between the oscillator and the reference, and an unwanted high-frequency signal that is filtered out. If the phase shift is zero, no pulses are generated. A bang-bang type configuration uses current pulses, known as up-pulses or down-pulses. These pulses are sent with a fixed positive or negative charge of constant width to a capacitor acting as a low-pass filter. Similar to a linear detector, a bang-bang phase detector does not generate a pulse for a phase shift of zero. In a typical 0/180 linear phase detector, the pulses are only generated when the phase error is detected. Therefore, when the signals are in phase, the system does not generate any corrective pulses. The smaller the phase error, the narrower the up and down pulses. At increasingly high frequencies, these corrective pulses essentially disappear due to rise and fall time limitations and do not correct the shift in phase between the reference signal and the feedback signal. These detectors, even if designed to operate in linear mode, actually replicate a bang-bang type for most of the phase error range, particularly at high operating frequencies.